The present invention relates to the fabrication of semiconductor devices. More particularly, the present invention relates to the fabrication of a shallow trench isolation structure that advantageously reduces hot carrier reliability problems in the support circuit area of a dynamic random access memory (DRAM) while maintaining a high retention time in the array area of the DRAM.
Dynamic random access memory is known in the art. Generally speaking, a dynamic random access memory includes an array area which typically has transistors and capacitors. The capacitors are typically configured to store a charge which can be accessed by appropriate support circuitry associated with the DRAM. Typically, the array circuitry and the support circuitry of the DRAM are located in different areas of the integrated circuit (IC). Although transistors are present in both the array area and the support area of the DRAM, N-FETs (N-channel Field Effect Transistors) are typically employed in the array area, while P-FETs (P-channel Field Effect Transistors) are generally employed in the support circuitry area.
The transistors are typically implemented in wells which are created in the substrate of the integrated circuit die. These wells are separated, in some circuits, by shallow trench isolation structures. To facilitate discussion, FIG. 1 illustrates a shallow trench isolation structure 100 which is created in a silicon substrate 102. Above surface 110 of silicon substrate 102, a pad oxide layer 106 is deposited. Above pad oxide layer 106 is disposed a pad nitride layer 108. After pad oxide layer 106 and pad nitride layer 108 are deposited above surface 110 of silicon substrate 102, a photoresist layer (not shown) is then formed above pad nitride layer 108 to facilitate etching of trench 104. The etchant will etch through pad nitride layer 108, pad oxide layer 106 and into silicon substrate 102. The depth to which the trench is etched may vary with particular DRAM designs, however the trench depth is typically about 2000 to 3000 angstroms below the silicon surface. Thereafter, an active area oxide layer 112 is formed on the vertical surfaces of trench 104. After the formation of active area oxide layer 112, a nitride liner 114 is conformably deposited in trench 104 and above pad nitride layer 108.
In FIG. 2, an oxide fill 202, typically comprising tetraethylorthosilicate (TEOS), is deposited into trench 104 and planarized so that the top surface of oxide fill 202 lies substantially planar with the top surface of the nitride liner 114. Thereafter, the portion of nitride liner 114 lying above pad nitride layer 108, and pad nitride layer 108 are stripped away.
To completely strip away thick pad nitride layer 108, some overetching of the remaining portion of nitride liner 114 may occur, which causes the remaining portion of nitride liner 114 to be recessed inside trench 104. The recessed nitride liner 114 is shown in FIG. 3A in which pad nitride layer 108 has been stripped away and nitride liner 114 has been recessed so that the top surface of nitride liner 114 is now within trench 104. Consequently, the recess of nitride liner 114 creates a divot region 302 within the trench as shown. In one example such overetching may result in the recess of nitride liner 114, and therefore the divot region 302, having a depth of about 200 angstroms.
Thereafter, subsequent gate forming processes are performed in which, after planarizing the oxide fill 202, the gate oxide 304 and gate polysilicon 306 are deposited to form a transistor gate as shown in FIG. 3B. As is well known to those skilled in the art, some of the gate polysilicon material will be deposited into divot region 302 thereby wrapping around the silicon portions which are isolated by the STI.
It is difficult to control the depth of the divot region (shown in FIG. 3A as 302) created by the etch process employed to strip pad nitride layer 108. Since the gate polysilicon is subsequently deposited into this divot region, the variable depth of divot region 302 leads to a variable amount of polysilicon wrapped around the gate. This affects control of the threshold voltage of the gate to be formed, thereby degrading performance of the transistors (e.g., the N-FET transistors in the DRAM array area).
Although not shown in FIGS. 1-3, shallow trench isolation structure 100 is typically disposed beside a capacitor located in the array area of the DRAM. The capacitor typically extends below the substrate surface to a depth greater than approximately 5000 nanometers (nm). The capacitor typically includes an isolation oxide region, also know as a collar oxide, which typically extends to a depth of 1500 nm below the surface of the substrate. A portion of the bottom surface of the STI becomes juxtaposed with the collar oxide. Following the deposition of oxide fill 202, subsequent high temperature process steps, for example shallow trench TEOS fill densification, may be employed. The presence of nitride liner 114 helps prevent unwanted oxidation of the collar oxide of the capacitor during such high temperature steps. As is well known in the art, such unwanted oxidation causes dislocations in the silicon, thereby affecting the retention time, i.e., the ability of the capacitor in the array area to hold a charge.
However, the proximity of nitride liner 114 to the transistor channels disadvantageously exacerbates the hot carrier reliability problem for the P-FET transistors in the support circuitry. Hot carrier reliability problems are caused when nitride liner 114 traps or collects charge that should traverse the P-FET channels located near the shallow trench isolation structure. Such trapping or collecting may occur when a portion of nitride liner 114 lies at a depth less than the P-FET channel depth Dc as shown in FIG. 3A. By way of example, the recessed nitride liner overlaps the P-FET channel by about 800 angstroms in FIG. 3A. As can be appreciated by those skilled in the art, hot carrier reliability problems increase power consumption of the P-FET transistors and, in some cases, may lead to incorrect timing of the circuitry.
In view of the foregoing, there are desired improved shallow trench isolation structures which advantageously reduce hot carrier reliability problems in the support circuit area of a dynamic random access memory (DRAM) while maintaining a high retention time in the array area of the DRAM.